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1996 data sheet mos integrated circuit m pd784031y 16-/8-bit single-chip microcontrollers the m pd784031y is based on the m pd784031 with an i 2 c bus control function appended, and is ideal for applications in audio-visual systems. the m pd784031y is a rom-less version of m pd784035y and 784036y. the functions are explained in detail in the following users manual. be sure to read this manual when designing your system. m pd784038, 784038y subseries users manual - hardware : u11316e 78k/iv series users manual - instruction : u10905e timer/counter 16-bit timer/counter x 3 units 16-bit timer x 1 unit standby function halt/stop/idle mode clock division function watchdog timer: 1 channel a/d converter: 8-bit resolution x 8 channels d/a converter: 8-bit resolution x 2 channels supply voltage: v dd = 2.7 to 5.5 v features 78k/iv series pin-compatible with m pd78234 subseries, m pd784026 subseries, and m pd784038 subseries minimum instruction execution time: 125 ns (@ 32-mhz operation) i/o ports: 46 serial interface: 3 channels uart/ioe (3-wire serial i/o): 2 channels csi (3-wire serial i/o, 2-wire serial i/o, i 2 c bus): 1 channel pwm output: 2 outputs application fields cellular phones, cordless phones, audio-visual systems, etc. ordering information part number package internal rom (bytes) internal ram (bytes) m pd784031ygc-3b9 80-pin plastic qfp (14 x 14 mm, thickness 2.7 mm) none 2048 m pd784031ygc-8bt 80-pin plastic qfp (14 x 14 mm, thickness 1.4 mm) none 2048 m pd784031ygk-be9 80-pin plastic tqfp (fine pitch) (12 x 12 mm) none 2048 the information in this document is subject to change without notice. document no. u11504ej1v0ds00 (1st edition) date published july 1997 n printed in japan the mark shows major revised points.
2 m pd784031y 78k/iv series product development pd784026 pd784038y i 2 c bus supported pd784038 enhanced internal memory capacity, pin compatible with the pd784026 pd784225y multimaster i 2 c bus supported pd784225 80 pins, added rom correction pd784218y multimaster i 2 c bus supported multimaster i 2 c bus supported pd784218 enhanced internal memory capacity, added rom correction pd784928y multimaster i 2 c bus supported pd784928 enhanced function of the pd784915 pd784216y pd784054 pd784216 pd784046 pd784908 equipped with 10-bit a/d 100 pins, enhanced i/o and internal memory capacity enhanced a/d, 16-bit timer, and power management pd784915 equipped with analog circuit for software servo control vcr, enhanced timer equipped with iebus tm controller pd78f4943 for cd-rom, 56-kbyte flash memory standard models assp models : under mass production : under development
3 m pd784031y functions item function number of basic instructions 113 (mnemonics) general-purpose register 8 bits x 16 registers x 8 banks, or 16 bits x 8 registers x 8 banks (memory mapping) minimum instruction execution 125 ns/250 ns/500 ns/1000 ns (at 32 mhz) time internal memory rom none ram 2048 bytes memory space 1 mbytes with program and data spaces combined i/o port total 46 input 8 i/o 34 output 4 pins with pull- 32 up resistor leds direct 8 drive output transistor 8 direct drive real-time output port 4 bits x 2, or 8 bits x 1 timer/counter timer/counter 0: timer register x 1 pulse output capture register x 1 ? toggle output compare register x 2 ? pwm/ppg output (16 bits) ? one-shot pulse output timer/counter 1: timer register x 1 pulse output capture register x 1 ? real-time output (4 bits x 2) (8/16 bits) capture/compare register x 1 compare register x 1 timer/counter 2: timer register x 1 pulse output capture register x 1 ? toggle output (8/16 bits) capture/compare register x 1 ? pwm/ppg output compare register x 1 timer 3: timer register x 1 (8/16 bits) compare register x 1 pwm output 12-bit resolution x 2 channels serial interface uart/ioe (3-wire serial i/o) : 2 channels (on-chip baud rate generator) csi (3-wire serial i/o, 2-wire serial i/o, i 2 c bus) : 1 channel a/d converter 8-bit resolution x 8 channels d/a converter 8-bit resolution x 2 channels watchdog timer 1 channel standby halt/stop/idle mode interrupt hardware source 24 (internal: 17, external: 7 (variable sampling clock input: 1)) software source brk instruction, brkcs instruction, operand error non-maskable internal: 1, external: 1 maskable internal: 16, external: 6 ? 4 programmable priority levels ? 3 processing styles: vectored interrupt/macro service/context switching supply voltage v dd = 2.7 to 5.5 v package 80-pin plastic qfp (14 x 14 mm, thickness 2.7 mm) 80-pin plastic qfp (14 x 14 mm, thickness 1.4 mm) 80-pin plastic tqfp (fine pitch) (12 x 12 mm) note the pins with ancillary function are included in the i/o pins. pins with ancillary function note
4 m pd784031y contents 1. differences among models in m pd784038y subseries .................................................. 6 2. major differences from m pd784026 subseries and m pd78234 subseries .............. 7 3. pin configuration (top view) ............................................................................................... .... 8 4. block diagram .............................................................................................................. .............. 10 5. pin function ................................................................................................................. .............. 11 5.1 port pins ................................................................................................................... ............................. 11 5.2 non-port pins ............................................................................................................... ......................... 12 5.3 types of pin i/o circuits and connections for unused pins ............................................................ 14 6. cpu architecture ............................................................................................................. ....... 17 6.1 memory space ................................................................................................................ ....................... 17 6.2 cpu registers ............................................................................................................... ........................ 19 6.2.1 general-purpose registers ................................................................................................. ......... 19 6.2.2 control registers ......................................................................................................... ................. 20 6.2.3 special function registers (sfrs) ......................................................................................... ...... 21 7. peripheral hardware functions ..................................................................................... 26 7.1 ports ....................................................................................................................... ................................ 26 7.2 clock generation circuit .................................................................................................... .................. 27 7.3 real-time output port ....................................................................................................... .................... 29 7.4 timer/counter ............................................................................................................... ......................... 30 7.5 pwm output (pwm0, pwm1) ..................................................................................................... ........... 32 7.6 a/d converter ............................................................................................................... ......................... 33 7.7 d/a converter ............................................................................................................... ......................... 34 7.8 serial interface ............................................................................................................ .......................... 35 7.8.1 asynchronous serial interface/3-wire serial i/o (uart/ioe) ...................................................... 36 7.8.2 clocked serial interface (csi) ............................................................................................ ......... 38 7.9 edge detection function ..................................................................................................... ................. 39 7.10 watchdog timer ............................................................................................................. ....................... 40 8. interrupt function ........................................................................................................... ...... 41 8.1 interrupt sources ........................................................................................................... ....................... 41 8.2 vectored interrupt .......................................................................................................... ....................... 43 8.3 context switching ........................................................................................................... ...................... 44 8.4 macro service ............................................................................................................... ......................... 44 8.5 application example of macro service ........................................................................................ ....... 45
5 m pd784031y 9. local bus interface .......................................................................................................... .... 47 9.1 memory expansion ............................................................................................................ ................... 47 9.2 memory space ................................................................................................................ ....................... 48 9.3 programmable wait ........................................................................................................... ................... 49 9.4 pseudo static ram refresh function .......................................................................................... ....... 49 9.5 bus hold function ........................................................................................................... ..................... 49 10. standby function ............................................................................................................ ........ 50 11. reset function .............................................................................................................. ........... 51 12. instruction set ............................................................................................................. ........... 52 13. electrical specifications ................................................................................................... 57 14. package drawings ............................................................................................................ ...... 77 15. recommended soldering conditions .............................................................................. 80 appendix a. development tools ............................................................................................... 82 appendix b. related documents ............................................................................................... 84
6 m pd784031y 1. differences among models in m pd784038y subseries the only difference among the m pd784031y, 784035y, 784036y, 784037y, and 784038y lies in the internal memory capacity. the m pd78p4038y is provided with a 128-kbyte one-time prom or eprom instead of the mask rom of the m pd784035y, 784036y, 784037y, and 784038y. these differences are summarized in table 1-1. table 1-1. differences among models in m pd784038y subseries part number m pd784031y m pd784035y m pd784036y m pd784037y m pd784038y m pd78p4038y item internal rom none 48 kbytes 64 kbytes 96 kbytes 128 kbytes 128 kbytes (mask rom) (mask rom) (mask rom) (mask rom) (one-time prom or eprom) internal ram 2048 bytes 3584 bytes 4352 bytes package 80-pin plastic qfp (14 x 14 mm, thickness 2.7 mm) 80-pin plastic qfp (14 x 14 mm, thickness 1.4 mm) 80-pin plastic tqfp (fine pitch) (12 x 12 mm) 80-pin ceramic wqfn (14 x 14 mm)
7 m pd784031y 2. major differences from m pd784026 subseries and m pd78234 subseries series name m pd784038y subseries m pd784026 subseries m pd78234 subseries item m pd784038 subseries number of basic instructions 113 65 (mnemonics) minimum instruction execution time 125 ns 160 ns 333 ns (@ 32-mhz operation) (@ 25-mhz operation) (@ 12-mhz operation) memory space (program/data) 1 mbytes combined 64 kbytes/1 mbytes timer/counter 16-bit timer/counter x 1 16-bit timer/counter x 1 8-/16-bit timer/counter x 2 8-bit timer/counter x 2 8-/16-bit timer x 1 8-bit timer x 1 clock output function provided none watchdog timer provided none serial interface interrupt context provided none switching priority 4 levels 2 levels standby function halt/stop/idle mode halt/stop mode operating clock selectable from f xx /2, f xx /4, f xx /8, and f xx /16 fixed to f xx /2 pin function mode pin none specifies rom-less mode (always high level with m pd78233 and 78237) test pin device test pin none usually, low level package note m pd784038y subseries only uart/ioe (3-wire serial i/o) x 2 channels csi (3-wire serial i/o, 2-wire serial i/o, i 2 c bus note ) x 1 channel uart/ioe (3-wire serial i/o) x 2 channels csi (3-wire serial i/o, sbi) x 1 channel uart x 1 channel csi (3-wire serial i/o, sbi) x 1 channel 80-pin plastic qfp (14 x 14 mm, thickness 2.7 mm) 80-pin plastic qfp (14 x 14 mm, thickness 1.4 mm) 80-pin plastic tqfp (fine pitch) (12 x 12 mm) 80-pin ceramic wqfn (14 x 14 mm): m pd78p4038y and 78p4038 only 80-pin plastic qfp (14 x 14 mm, thickness 2.7 mm) 80-pin plastic tqfp (fine pitch) (12 x 12 mm): m pd784021 only 80-pin ceramic wqfn (14 x 14 mm): m pd78p4026 only 80-pin plastic qfp (14 x 14 mm, thickness 2.7 mm) 94-pin plastic qfp (20 x 20 mm) 84-pin plastic qfj (1150 x 1150 mil) 94-pin ceramic wqfn (20 x 20 mm): m pd78p238 only
8 m pd784031y 3. pin configuration (top view) ? 80-pin plastic qfp (14 x 14 mm, thickness 2.7 mm) m pd784031ygc-3b9 ? 80-pin plastic qfp (14 x 14 mm, thickness 1.4 mm) m pd784031ygc-8bt ? 80-pin plastic tqfp (fine pitch) (12 x 12 mm) m pd784031ygk-be9 note directly connect the test pin to v ss0 . 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 80 61 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 21 40 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 p32/sck0/scl p33/so0/sda p34/to0 p35/to1 p36/to2 p37/to3 reset v dd1 x2 x1 v ss1 p00 p01 p02 p03 p04 p05 p06 p07 p67/refrq/hldak p74/ani4 p73/ani3 p72/ani2 p71/ani1 p70/ani0 v dd0 p17 p16 p15 p14/txd2/so2 p13/txd2/si2 p12/asck2/sck2 p11/pwm1 p10/pwm0 test note v ss0 astb ad0 ad1 ad2 p31/txd/so1 p30/rxd/si1 p27/si0 p26/intp5 p25/intp4/asck/sck1 p24/intp3 p23/intp2/ci p22/intp1 p21/intp0 p20/nmi av ref3 av ref2 ano1 ano0 av ss av ref1 av dd p77/ani7 p76/ani6 p75/ani5 p66/wait/hldrq wr rd p63/a19 p62/a18 p61/a17 p60/a16 a15 a14 a13 a12 a11 a10 a9 a8 ad7 ad6 ad5 ad4 ad3
9 m pd784031y a8 to a19 : address bus ad0 to ad7 : address/data bus ani0 to ani7 : analog input ano0, ano1 : analog output asck, asck2 : asynchronous serial clock astb : address strobe av dd : analog power supply av ref1 to av ref3 : reference voltage av ss : analog ground ci : clock input hldak : hold acknowledge hldrq : hold request intp0 to intp5 : interrupt from peripherals nmi : non-maskable interrupt p00 to p07 : port0 p10 to p17 : port1 p20 to p27 : port2 p30 to p37 : port3 p60 to p63, p66, p67 : port6 p70 to p77 : port7 pwm0, pwm1 : pulse width modulation output rd : read strobe refrq : refresh request reset : reset rxd, rxd2 : receive data sck0 to sck2 : serial clock scl : serial clock sda : serial data si0 to si2 : serial input so0 to so2 : serial output test : test to0 to to3 : timer output txd, txd2 : transmit data v dd0 , v dd1 : power supply v ss0 , v ss1 : ground wait : wait wr : write strobe x1, x2 : crystal
10 m pd784031y 4. block diagram programmable interrupt controller timer/counter0 (16 bits) timer/counter1 (16 bits) timer/counter2 (16 bits) timer3 (16 bits) real-time output port pwm d/a converter a/d converter 78k/iv cpu core ram watchdog timer uart/ioe2 baud-rate generator uart/ioe1 baud-rate generator clocked serial interface bus i/f port0 port1 port2 port3 port6 port7 system control nmi intp0 to intp5 intp3 to0 to1 intp0 intp1 intp2/ci to2 to3 p00 to p03 p04 to p07 pwm0 pwm1 ano0 ano1 av ref2 av ref3 ani0 to ani7 av dd av ref1 av ss intp5 rxd/si1 txd/so1 asck/sck1 rxd2/si2 txd2/so2 asck2/sck2 sck0/scl so0/sda si0 astb ad0 to ad7 a8 to a15 a16 to a19 rd wr wait/hldrq refrq/hldak p00 to p07 p10 to p17 p20 to p27 p30 to p37 p70 to p77 p60 to p63 p66 to p67 reset test x1 x2 v dd0, v dd1 v ss0, v ss1
11 m pd784031y 5. pin function 5.1 port pins pin name i/o alternate function function p00 to p07 i/o C p10 i/o pwm0 p11 pwm1 p12 asck2/sck2 p13 rxd2/si2 p14 txd2/so2 p15 to p17 C p20 input nmi p21 intp0 p22 intp1 p23 intp2/ci p24 intp3 p25 intp4/asck/sck1 p26 intp5 p27 si0 p30 i/o rxd/s1 p31 txd/so1 p32 sck0/scl p33 so0/sda p34 to p37 to0 to to3 p60 to p63 i/o a16 to a19 p66 wait/hldrq p67 refrq/hldak p70 to p77 i/o an10 to an17 port 1 (p1): ? 8-bit i/o port ? can be set in input or output mode bitwise. ? pins set in input mode can be connected to internal pull-up resistors by software. ? can drive leds. port 2 (p2): ? 8-bit input port ? p20 cannot be used as general-purpose port pin (non-maskable interrupt). however, its input level can be checked by interrupt routine. ? p22 through p27 can be connected to internal pull-up resistors by software in 6-bit units. ? p25/intp4/asck/sck1 pin can operate as sck1 output pin if so specified by csim1. port 3 (p3): ? 8-bit i/o port ? can be set in input or output mode bitwise. ? pins set in input mode can be connected to internal pull-up resistors by software. port 6 (p6): ? p60 through p63 is dedicated ports for output. ? p66 and p67 can be set in input or output mode bitwise. ? pins set in input mode can be connected to internal pull-up resistors by software. port 0 (p0): ? 8-bit i/o port ? can be used as real-time output port (4 bits x 2). ? can be set in input or output mode bitwise. ? pins set in input mode can be connected to internal pull-up resistors by software. ? can drive transistor. port 7 (p7): ? 8-bit i/o port ? can be set in input or output mode bitwise.
12 m pd784031y 5.2 non-port pins pin name i/o alternate function function to0 to to3 output p34 to p37 timer output ci input p23/intp2 count clock input to timer/counter 2 rxd input p30/si1 serial data input (uart0) rxd2 p13/si2 serial data input (uart2) txd output p31/so1 serial data output (uart0) txd2 p14/so2 serial data output (uart2) asck input p25/intp4/sck1 baud rate clock input (uart0) asck2 p12/sck2 baud rate clock input (uart2) sda i/o p33/so0 serial data input/output (2-wire serial i/o, i 2 c bus) si0 input p27 serial data input (3-wire serial i/o0) si1 p30/rxd serial data input (3-wire serial i/o1) si2 p13/rxd2 serial data input (3-wire serial i/o2) so0 output p33/sda serial data output (3-wire serial i/o0) so1 p31/txd serial data output (3-wire serial i/o1) so2 p14/txd2 serial data output (3-wire serial i/o2) sck0 i/o p32/scl serial clock input/output (3-wire serial i/o0) sck1 p25/intp4/asck serial clock input/output (3-wire serial i/o1) sck2 p12/asck2 serial clock input/output (3-wire serial i/o2) scl p32/sck0 serial clock input/output (2-wire serial i/o, i 2 c bus) nmi input p20 external interrupt requests C intp0 p21 ? count clock input to timer/counter 1 ? capture trigger signal of cr11 or cr12 intp1 p22 ? count clock input to timer/counter 2 ? capture trigger signal of cr22 intp2 p23/ci ? count clock input to timer/counter 2 ? capture trigger signal of cr21 intp3 p24 ? count clock input to timer/counter 0 ? capture trigger signal of cr02 intp4 p25/asck/sck1 C intp5 p26 conversion start trigger input to a/d converter ad0 to ad7 i/o C time-division address/data bus (for external memory connection) a8 to a15 output C higher address bus (for external memory connection) a16 to a19 output p60 to p63 higher address when address is extended (for external memory connection) rd output C read strobe to external memory wr output C write strobe to external memory wait input p66/hldrq wait insertion refrq output p67/hldak refresh pulse output to external pseudo static memory hldrq input p66/wait bus hold request input hldak output p67/refrq bus hold acknowledge output astb output C latch timing output of time-division address (a0 through a7) (when accessing external memory)
13 m pd784031y pin name i/o alternate function function reset input C chip reset x1 input C crystal connection for system clock oscillation x2 C (clock can also be input to x1.) ani0 to ani7 input p70 to p77 analog voltage input to a/d converter ano0, ano1 output C analog voltage output from d/a converter av ref1 C C reference voltage to a/d converter av ref2 , av ref3 reference voltage to d/a converter av dd a/d converter power supply av ss a/d converter gnd v dd0 note 1 power supply of port v dd1 note 1 power supply except for port v ss0 note 2 gnd of port v ss1 note 2 gnd except for port test directly connect to v ss0 (ic test pin). notes 1. provide the same potential to v dd0 and v dd1 . 2. provide the same potential to v ss0 and v ss1 .
14 m pd784031y 5.3 types of pin i/o circuits and connections for unused pins table 5-1 shows types of pin i/o circuits and the connections for unused pins. for the input/output circuit of each type, refer to figure 5-1. table 5-1. types of pin i/o circuits and connections for unused pins (1/2) pin name i/o circuit type i/o recommended connection for unused pins p00 to p07 5-h i/o input: connect to v dd0 . p10/pwm0 output: open p11/pwm1 p12/asck2/sck2 8-c p13/rxd2/si2 5-h p14/txd2/so2 p15 to p17 p20/nmi 2 input connect to v dd0 or v ss0 . p21/intp0 p22/intp1 2-c connect to v dd0 . p23/intp2/ci p24/intp3 p25/intp4/asck/sck1 8-c i/o input: connect to v dd0 . output: open p26/intp5 2-c input connect to v dd0 . p27/si0 p30/rxd/si1 5-h i/o input: connect to v dd0 . p31/txd/so1 output: open p32/sck0/scl 10-b p33/so0/sda p34/to0 to p37/to3 5-h ad0 to ad7 a8 to a15 output note open p60/a16 to p63/a19 rd wr p66/wait/hldrq i/o input: connect to v dd0 . p67/refrq/hldak output: open p70/ani0 to p77/ani7 20-a input: connect to v dd0 or v ss0 . output: open ano0, ano1 12 output open astb 4-b note i/o circuit type of these pins is 5-h. however these pins perform only as output by an internal circuit.
15 m pd784031y table 5-1. types of pin i/o circuits and connections for unused pins (2/2) pin name i/o circuit type i/o recommended connection for unused pins reset 2 input C test 1-a directly connect to v ss0 . av ref1 to av ref3 C connect to v ss0 . av ss av dd connect to v dd0 . caution connect an i/o pin whose input/output mode is unstable to v dd0 via a resistor of several 10 k w (especially if the voltage on the reset input pin rises higher than the low-level input level on power application or when the mode is switched between input and output by software). remark because the circuit type numbers shown in the above table are commonly used with all the models in the 78k series, these numbers of some models are not serial (because some circuits are not provided to some models).
16 m pd784031y figure 5-1. types of pin i/o circuits type 2 type 1-a type 4-b type 5-h p in v dd0 v ss0 n in data output disable p out v dd0 v ss0 n data output disable p in/out v dd0 v ss0 n input enable p v dd0 pullup enable type 2-c in p v dd0 pullup enable type 8-c type 10-b data output disable p in/out v dd0 n p v dd0 v ss0 pullup enable data output disable p in/out v dd0 n p v dd0 v ss0 pullup enable open drain type 12 p n out type 20-a data output disable p in/out v dd0 v ss0 av ss n input enable + p n av ref (threshold voltage) schmitt trigger input with hysteresis characteristics push-pull output that can go into a high-impedance state (with both p-ch and n-ch off) schmitt trigger input with hysteresis characteristics analog output voltage comparator
17 m pd784031y 6. cpu architecture 6.1 memory space a memory space of 1 mbytes can be accessed. mapping of the internal data area (special function registers and internal ram) can be specified the location instruction. the location instruction must be always executed after reset cancellation, and must not be used more than once. (1) when location 0 instruction is executed the internal data area is mapped in 0f700h to 0ffffh. (2) when location 0fh instruction is executed the internal data area is mapped in ff700h to fffffh.
18 m pd784031y figure 6-1. memory map of m pd784031y note base area and entry area for reset or interrupt. however, the internal ram area is not used as a reset entry area. (256 bytes) special function registers (sfr) external memory (63232 bytes) internal ram (2 kbytes) external memory (960 kbytes) general-purpose registers (128 bytes) macro service control word area (44 bytes) data area (512 bytes) program/data area (1536 bytes) callf entry area (2 kbytes) callt table area (64 bytes) vector table area (64 bytes) internal ram (2 kbytes) external memory (1046272 bytes) (256 bytes) on execution of location 0 instruction special function registers (sfr) on execution of location 0fh instruction h f f f f f h 0 0 0 0 1 h f f f f 0 h f d f f 0 h 0 d f f 0 h 0 0 f f 0 h f f e f 0 h 0 0 d f 0 h f f c f 0 h 0 0 7 f 0 h f f 6 f 0 h 0 0 0 0 0 h f f e f 0 h 0 8 e f 0 h f 7 e f 0 h 1 3 e f 0 h 0 0 d f 0 h f f c f 0 h 6 0 e f 0 h 0 0 7 f 0 h 0 0 0 1 0 h f f f 0 0 h 0 0 8 0 0 h f f 7 0 0 h 0 8 0 0 0 h f 7 0 0 0 h 0 4 0 0 0 h f 3 0 0 0 h 0 0 0 0 0 h f f e f f h 0 8 e f f h f 7 e f f h e f f h 6 0 e f f h 0 0 d f f h f f c f f h 0 0 7 f f h 0 0 0 0 0 h f f f 0 0 h 0 0 8 0 0 h f f 7 0 0 h 0 8 0 0 0 h f 7 0 0 0 h f f f f 0 h 0 0 0 0 1 h f f 6 f f h 0 0 7 f f h f f f f f h f d f f f h 0 d f f f h 0 0 f f f h f f e f f note note 1 3
19 m pd784031y 6.2 cpu registers 6.2.1 general-purpose registers sixteen 8-bit general-purpose registers are available. two 8-bit registers can be also used in pairs as a 16-bit register. of the 16-bit registers, four can be used in combination with an 8-bit register for address expansion as 24-bit address specification registers. eight banks of these registers are available which can be selected by using software or the context switching function. the general-purpose registers except v, u, t, and w registers for address expansion are mapped to the internal ram. figure 6-2. general-purpose register format caution registers r4, r5, r6, r7, rp2, and rp3 can be used as x, a, c, b, ax, and bc registers, respectively, by setting the rss bit of the psw to 1. however, use this function only for recycling the program of the 78k/iii series. a (r1) b (r3) r5 r7 r9 r11 d (r13) h (r15) v u t w vvp (rg4) uup (rg5) tde (rg6) whl (rg7) x (r0) c (r2) r4 r6 r8 r10 e (r12) l (r14) ax (rp0) bc (rp1) rp2 rp3 vp (rp4) up (rp5) de (rp6) hl (rp7) parentheses ( ) indicate an absolute name. 8 banks
20 m pd784031y 6.2.2 control registers (1) program counter (pc) the program counter is a 20-bit register whose contents are automatically updated when the program is executed. figure 6-3. program counter (pc) format (2) program status word (psw) this register holds the statuses of the cpu. its contents are automatically updated when the program is executed. figure 6-4. program status word (psw) format note this flag is provided to maintain compatibility with the 78k/iii series. be sure to clear this flag to 0, except when the software for the 78k/iii series is used. (3) stack pointer (sp) this is a 24-bit pointer that holds the first address of the stack. be sure to write 0 to the higher 4 bits of this pointer. figure 6-5. stack pointer (sp) format 19 0 pc 15 14 13 12 11 10 9 8 uf rbs2 rbs1 rbs0 pswh 76 54 3210 s z rss note ac ie p/v 0 cy pswl psw 23 0 sp 20 0 0 0 0
21 m pd784031y 6.2.3 special function registers (sfrs) the special function registers, such as the mode registers and control registers of the internal peripheral hardware, are registers to which special functions are allocated. these registers are mapped to a 256-byte space of addresses 0ff00h through 0ffffh note . note on execution of the location 0 instruction. fff00h through fffffh on execution of the location 0fh instruction. caution do not access an address in this area to which no sfr is allocated. if such an address is accessed by mistake, the m pd784031y may be in the deadlock status. this deadlock status can be cleared only by inputting the reset signal. table 6-1 lists the special function registers (sfrs). the meanings of the symbols in this table are as follows: ? symbol ................................ symbol indicating an sfr. this symbol is reserved for necs assembler (ra78k4). it can be used as an sfr variable by the #pragma sfr command with the c compiler (cc78k4). ? r/w ..................................... indicates whether the sfr is read-only, write-only, or read/write. r/w : read/write r : read-only w : write-only ? bit units for manipulation .... bit units in which the value of the sfr can be manipulated. sfrs that can be manipulated in 16-bit units can be described as the operand sfrp of an instruction. to specify the address of this sfr, describe an even address. sfrs that can be manipulated in 1-bit units can be described as the operand of a bit manipulation instruction. ? after reset ........................... indicates the status of the register when the reset signal has been input.
22 m pd784031y table 6-1. special function registers (sfrs) (1/4) address note special function register (sfr) name symbol r/w bit units for manipulation after reset 1 bit 8 bits 16 bits 0ff00h port 0 p0 r/w ?? C undefined 0ff01h port 1 p1 ?? C 0ff02h port 2 p2 r ?? C 0ff03h port 3 p3 r/w ?? C 0ff06h port 6 p6 ?? C 00h 0ff07h port 7 p7 ?? C undefined 0ff0eh port 0 buffer register l p0l ?? C 0ff0fh port 0 buffer register h p0h ?? C 0ff10h compare register (timer/counter 0) cr00 C C ? 0ff12h capture/compare register (timer/counter 0) cr01 C C ? 0ff14h compare register l (timer/counter 1) cr10 cr10w C ?? 0ff15h compare register h (timer/counter 1) C C C 0ff16h capture/compare register l (timer/counter 1) cr11 cr11w C ?? 0ff17h capture/compare register h (timer/counter 1) C C C 0ff18h compare register l (timer/counter 2) cr20 cr20w C ?? 0ff19h compare register h (timer/counter 2) C C C 0ff1ah capture/compare register l (timer/counter 2) cr21 cr21w C ?? 0ff1bh capture/compare register h (timer/counter 2) C C C 0ff1ch compare register l (timer 3) cr30 cr30w C ?? 0ff1dh compare register h (timer 3) C C C 0ff20h port 0 mode register pm0 ?? C ffh 0ff21h port 1 mode register pm1 ?? C 0ff23h port 3 mode register pm3 ?? C 0ff26h port 6 mode register pm6 ?? C 0ff27h port 7 mode register pm7 ?? C 0ff2eh real-time output port control register rtpc ?? C 00h 0ff30h capture/compare control register 0 crc0 C ? C 10h 0ff31h timer output control register toc ?? C 00h 0ff32h capture/compare control register 1 crc1 C ? C 0ff33h capture/compare control register 2 crc2 C ? C 10h note when the location 0 instruction is executed. when the location 0fh instruction is executed, f0000h is added to this value.
23 m pd784031y table 6-1. special function registers (sfrs) (2/4) address note 1 special function register (sfr) name symbol r/w bit units for manipulation after reset 1 bit 8 bits 16 bits 0ff36h capture register (timer/counter 0) cr02 r C C ? 0000h 0ff38h capture register l (timer/counter 1) cr12 cr12w C ?? 0ff39h capture register h (timer/counter 1) C C C 0ff3ah capture register l (timer/counter 2) cr22 cr22w C ?? 0ff3bh capture register h (timer/counter 2) C C C 0ff41h port 1 mode control register pmc1 r/w ?? C 00h 0ff43h port 3 mode control register pmc3 ?? C 0ff4eh pull-up resistor option register puo ?? C 0ff50h timer register 0 tm0 r C C ? 0000h 0ff51h CC 0ff52h timer register 1 tm1 tm1w C ?? 0ff53h C C C 0ff54h timer register 2 tm2 tm2w C ?? 0ff55h C C C 0ff56h timer register 3 tm3 tm3w C ?? 0ff57h C C C 0ff5ch prescaler mode register 0 prm0 r/w C ? C 11h 0ff5dh timer control register 0 tmc0 ?? C 00h 0ff5eh prescaler mode register 1 prm1 C ? C 11h 0ff5fh timer control register 1 tmc1 ?? C 00h 0ff60h d/a conversion value setting register 0 dacs0 C ? C 0ff61h d/a conversion value setting register 1 dacs1 C ? C 0ff62h d/a converter mode register dam ?? C 03h 0ff68h a/d converter mode register adm ?? C 00h 0ff6ah a/d conversion result register adcr r C ? C undefined 0ff70h pwm control register pwmc r/w ?? C 05h 0ff71h pwm prescaler register pwpr C ? C 00h 0ff72h pwm modulo register 0 pwm0 C C ? undefined 0ff74h pwm modulo register 1 pwm1 C C ? 0ff7dh one-shot pulse output control register ospc ?? C 00h 0ff80h i 2 c bus control register iicc ?? C 0ff81h prescaler mode register for serial clock sprm C ? C 04h 0ff82h clocked serial interface mode register csim ?? C 00h 0ff83h slave address register sva r/w note 2 ? note 3 ? C 01h notes 1. when the location 0 instruction is executed. when the location 0fh instruction is executed, f0000h is added to this value. 2. bit 0 is read-only. 3. only bit 0 can be manipulated in bit units.
24 m pd784031y table 6-1. special function registers (sfrs) (3/4) address note 1 special function register (sfr) name symbol r/w bit units for manipulation after reset 1 bit 8 bits 16 bits 0ff84h clocked serial interface mode register 1 csim1 r/w ?? C 00h 0ff85h clocked serial interface mode register 2 csim2 ?? C 0ff86h serial shift register sio C ? C 0ff88h asynchronous serial interface mode register asim ?? C 0ff89h asynchronous serial interface mode register 2 asim2 ?? C 0ff8ah asynchronous serial interface status register asis r ?? C 0ff8bh asynchronous serial interface status register 2 asis2 ?? C 0ff8ch serial receive buffer: uart0 rxb C ? C undefined serial transmit shift register: uart0 txs w C ? C serial shift register: ioe1 sio1 r/w C ? C 0ff8dh serial receive buffer: uart2 rxb2 r C ? C serial transmit shift register: uart2 txs2 w C ? C serial shift register: ioe2 sio2 r/w C ? C 0ff90h baud rate generator control register brgc C ? C 00h 0ff91h baud rate generator control register 2 brgc2 C ? C 0ffa0h external interrupt mode register 0 intm0 ?? C 0ffa1h external interrupt mode register 1 intm1 ?? C 0ffa4h sampling clock select register scs0 C ? C 0ffa8h in-service priority register ispr r ?? C 0ffaah interrupt mode control register imc r/w ?? C 80h 0ffach interrupt mask register 0l mk0l mk0 ??? ffffh 0ffadh interrupt mask register 0h mk0h ?? 0ffaeh interrupt mask register 1l mk1l ?? C ffh 0ffc0h standby control register stbc C ? note 2 C 30h 0ffc2h watchdog timer mode register wdm C ? note 2 C 00h 0ffc4h memory expansion mode register mm ?? C 20h 0ffc5h hold mode register hldm ?? C 00h 0ffc6h clock output mode register clom ?? C 0ffc7h programmable wait control register 1 pwc1 C ? C aah 0ffc8h programmable wait control register 2 pwc2 C C ? aaaah notes 1. when the location 0 instruction is executed. when the location 0fh instruction is executed, f0000h is added to this value. 2. data can be written by using only dedicated instructions such as mov stbc, #byte and mov wdm, #byte, and cannot be written with any other instructions.
25 m pd784031y table 6-1. special function registers (sfrs) (4/4) address note special function register (sfr) name symbol r/w bit units for manipulation after reset 1 bit 8 bits 16 bits 0ffcch refresh mode register rfm r/w ?? C 00h 0ffcdh refresh area specification register rfa ?? C 0ffcfh oscillation stabilization time specification osts C ? C register 0ffd0h to external sfr area C ?? CC 0ffdfh 0ffe0h interrupt control register (intp0) pic0 ?? C 43h 0ffe1h interrupt control register (intp1) pic1 ?? C 0ffe2h interrupt control register (intp2) pic2 ?? C 0ffe3h interrupt control register (intp3) pic3 ?? C 0ffe4h interrupt control register (intc00) cic00 ?? C 0ffe5h interrupt control register (intc01) cic01 ?? C 0ffe6h interrupt control register (intc10) cic10 ?? C 0ffe7h interrupt control register (intc11) cic11 ?? C 0ffe8h interrupt control register (intc20) cic20 ?? C 0ffe9h interrupt control register (intc21) cic21 ?? C 0ffeah interrupt control register (intc30) cic30 ?? C 0ffebh interrupt control register (intp4) pic4 ?? C 0ffech interrupt control register (intp5) pic5 ?? C 0ffedh interrupt control register (intad) adic ?? C 0ffeeh interrupt control register (intser) seric ?? C 0ffefh interrupt control register (intsr) sric ?? C interrupt control register (intcsi1) csiic1 ?? C 0fff0h interrupt control register (intst) stic ?? C 0fff1h interrupt control register (intcsi) csiic ?? C 0fff2h interrupt control register (intser2) seric2 ?? C 0fff3h interrupt control register (intsr2) sric2 ?? C interrupt control register (intcsi2) csiic2 ?? C 0fff4h interrupt control register (intst2) stic2 ?? C 0fff5h interrupt control register (intspc) spcic ?? C note when the location 0 instruction is executed. when the location 0fh instruction is executed, f0000h is added to this value.
26 m pd784031y 7. peripheral hardware functions 7.1 ports the ports shown in figure 7-1 are provided to make various control operations possible. table 7-1 shows the function of each port. ports 0 through 6 can be connected to internal pull-up resistors by software when inputting. figure 7-1. port configuration port 0 port 1 port 3 port 6 port 7 port 2 p00 p07 p10 p17 p20 to p27 p30 p37 p60 p63 p70 p77 8 p66 p67
27 m pd784031y table 7-1. port functions port name pin name function specification of pull-up resistor connection by software port 0 p00 to p07 ? can be set in input or output mode in 1-bit units. all port pins in input mode ? can operate as 4-bit real-time output port (p00 through p03 and p04 through p07). ? can drive transistor. port 1 p10 to p17 ? can be set in input or output mode in 1-bit units. all port pins in input mode ? can drive leds. port 2 p20 to p27 ? input port in 6-bit units (p22 through p27) port 3 p30 to p37 ? can be set in input or output mode in 1-bit units. all port pins in input mode port 6 p60 to p63 ? output only all port pins in input mode p66, p67 ? can be set in input or output mode in 1-bit units. port 7 p70 to p77 ? can be set in input or output mode in 1-bit units. C 7.2 clock generation circuit an on-chip clock generation circuit necessary for operation is provided. this clock generation circuit has a divider circuit. if high-speed operation is not necessary, the internal operating frequency can be lowered by the divider circuit to reduce the current consumption. figure 7-2. block diagram of clock generation circuit x1 x2 f xx 1/2 1/2 1/2 1/2 uart/ioe intp0 noise reduction circuit oscillation stabilization timer f xx /2 f clk cpu peripheral circuit oscillation circuit selector remark f xx : oscillation frequency or external clock input f clk : internal operating frequency
28 m pd784031y figure 7-3. example of using oscillation circuit (1) crystal/ceramic oscillation (2) external clock extc bit of osts = 1 extc bit of osts = 0 caution when using the clock oscillation circuit, wire the dotted portion in the above figure as follows to avoid adverse influences of wiring capacitance. keep the wiring length as short as possible. do not cross the wiring with other signal lines. do not route the wiring in the vicinity of lines through which a high alternating current flows. always keep the potential at the ground point of the capacitor in the oscillation circuit the same as v ss1 . do not ground to a ground pattern through which a high current flows. do not extract signals from the oscillation circuit. pd784031y v ss1 x1 x2 m x1 x2 x1 x2 open pd784031y m pd784031y m pd74hc04, etc. m
29 m pd784031y 7.3 real-time output port the real-time output port outputs data stored in a buffer in synchronization with the coincidence interrupt generated by timer/counter 1 or with an external interrupt. as a result, pulses without jitter can be output. the real-time output port is therefore ideal for applications where arbitrary patterns must be output at specific intervals (such as open loop control of a stepping motor). the real-time output port mainly consists of port 0 and port 0 buffer registers (p0h and p0l) as shown in figure 7-4. figure 7-4. block diagram of real-time output port internal bus 844 44 8 real-time output port control register (rtpc) output trigger control circuit intp0 (from external source) intc10 (from timer/counter 1) intc11 (from timer/counter 1) p0h p0l buffer register output latch (p0) p07 p00
30 m pd784031y 7.4 timer/counter three units of timers/counters and one unit of timer are provided. because a total of seven interrupt requests are supported, these timers/counters and timer can be used as seven units of timers/counters. table 7-2. operations of timers/counters name timer/counter 0 timer/counter 1 timer/counter 2 timer 3 item count width 8 bits C ??? 16 bits ???? interval timer 2ch 2ch 2ch 1ch external event counter ??? C one-shot timer C C ? C function timer output 2ch C 2ch C toggle output ? C ? C pwm/ppg output ? C ? C one-shot pulse output note ? CCC real-time output C ? CC pulse width measurement 1 input 1 input 2 inputs C number of interrupt requests 2221 note the one-shot pulse output function makes a pulse output level active by software and inactive by hardware (interrupt request signal). this function is different in nature from the one-shot timer function of timer/counter 2. operation mode
31 m pd784031y figure 7-5. block diagram of timers/counters timer/counter 0 timer/counter 1 timer/counter 2 timer 3 remark ovf: overflow flag prescaler edge detection selector clear control timer register 0 (tm0) compare register (cr00) compare register (cr01) capture register (cr02) pulse output control ovf software trigger match to0 to1 intc00 intc01 intp3 intp3 f xx /8 prescaler edge detection selector clear control compare register (cr10/cr10w) capture/compare register (cr11/cr11w) capture register (cr12/cr12w) ovf intc10 intc11 intp0 intp0 f xx /8 event input timer register 1 (tm1/tm1w) prescaler edge detection selector clear control timer register 2 (tm2/tm2w) compare register (cr20/cr20w) capture/compare register (cr21/cr21w) capture register (cr22/cr22w) pulse output control ovf to2 to3 intc20 intc21 intp1 intp1 f xx /8 edge detection intp2 intp2/ci prescaler compare register (cr30/cr30w) match csi f xx /8 timer register 3 (tm3/tm3w) intc30 clear match match match match match to real-time output port
32 m pd784031y 7.5 pwm output (pwm0, pwm1) two channels of pwm (pulse width modulation) output circuits with a resolution of 12 bits and a repeat frequency of 62.5 khz (f clk = 16 mhz) are provided. both these pwm output channels can select a high or low level as the active level. these outputs are ideal for controlling the speed of a dc motor. figure 7-6. block diagram of pwm output unit remark n = 0 or 1 internal bus 16 8 reload control 4 8 8-bit down counter prescaler pulse control circuit 4-bit counter output control 1/256 pwmn (output pin) pwm control register (pwmc) 0 3 4 7 8 15 pwmn pwm modulo register f clk
33 m pd784031y 7.6 a/d converter an analog-to-digital (a/d) converter with eight multiplexed inputs (ani0 through ani7) is provided. this a/d converter is of successive approximation type. the result of conversion is retained by an 8-bit a/d conversion result register (adcr). therefore, high-speed, high-accuracy conversion can be performed (conversion time: approx. 7.5 m s at f clk = 16 mhz). a/d conversion can be started in either of the following two modes: ? hardware start: conversion is started by trigger input (intp5). ? software start: conversion is started by setting a bit of the a/d converter mode register (adm). after started, the a/d converter operates in the following modes: ? scan mode: two or more analog inputs are sequentially selected, and data to be converted are obtained from all the input pins. ? select mode: only one analog input pin is used to continuously obtain converted values. these operation modes and whether starting or stopping the a/d converter are specified by the adm. when the result of conversion is transferred to the adcr, interrupt request intad is generated. by using this request and macro service, the converted values can be successively transferred to the memory. figure 7-7. block diagram of a/d converter internal bus ani0 ani1 ani2 ani3 ani4 ani5 ani6 ani7 intp5 input selector edge detection circuit conversion trigger sample & hold circuit voltage comparator successive approximation register (sar) control circuit intad 8 series resistor string r/2 tap selector r r/2 av ref1 av ss 8 trigger enable a/d converter mode register (adm) 8 a/d conversion result register (adcr)
34 m pd784031y 7.7 d/a converter two circuits of digital-to-analog (d/a) converters are provided. these d/a converters are of voltage output type and have a resolution of 8 bits. the conversion method is of r-2r resistor ladder type. by writing a value to be output to an 8-bit d/a conversion value setting register (dacsn: n = 0 or 1), an analog value is output to the anon (n = 0 or 1) pin. the output voltage range is determined by the voltage applied across the av ref2 and av ref3 pins. because the output impedance is high, no current can be extracted from the output. if the impedance of the load is low, insert a buffer amplifier between the load and output pin. the anon pin goes into a high-impedance state while the reset signal is low. after releasing reset, dacsn is cleared to 0. figure 7-8. block diagram of d/a converter remark n = 0 or 1 av ref2 av ref3 anon 2r 2r r 2r r r 2r dacsn dacen internal bus selector
35 m pd784031y 7.8 serial interface three independent serial interface channels are provided. asynchronous serial interface (uart)/3-wire serial i/o (ioe) x 2 clocked serial interface (csi) x 1 ? 3-wire serial i/o (ioe) ? 2-wire serial i/o (ioe) ? i 2 c bus interface (i 2 c) therefore, communication with an external system and local communication within the system can be simultaneously executed (refer to figure 7-9 ). figure 7-9. example of serial interface (a) uart + i 2 c (b) uart + 3-wire serial i/o + 2-wire serial i/o note handshake line rs-232-c driver/receiver [uart] port rxd txd si so sck port int [3-wire serial i/o] so1 si1 sck1 intpm port sb0 sck0 port int note sda scl intpn port v dd v dd [2-wire serial i/o] pd784031y (master) m pd4711a m pd75108 (slave) m pd78014 (slave) m note pd784031y (master) pd4711a rs-232-c driver/receiver rs-232-c driver/receiver [uart] [uart] rxd txd rxd2 txd2 sda scl [i 2 c] lcd pd6272 (eeprom tm ) v dd sda scl sda scl v dd m pd4711a m m port port m pd78062y (slave) m
36 m pd784031y 7.8.1 asynchronous serial interface/3-wire serial i/o (uart/ioe) two channels of serial interfaces that can select an asynchronous serial interface mode and 3-wire serial i/o mode are provided. (1) asynchronous serial interface mode in this mode, data of 1 byte following the start bit is transferred or received. because an on-chip baud rate generator is provided, a wide range of baud rates can be set. moreover, the clock input to the asck pin can be divided to define a baud rate. when the baud rate generator is used, a baud rate conforming to the midi standard (31.25 kbps) can be also obtained. figure 7-10. block diagram in asynchronous serial interface mode remark f xx : oscillation frequency or external clock input n = 0 through 11 m = 16 through 30 1/2m 1/2m 1/2 n + 1 receive buffer rxb, rxb2 receive shift register transmit shift register receive control parity check transmit control parity append r x d, r x d2 t x d, t x d2 intsr, intsr2 intser, intser2 txs, txs2 intst, intst2 baud rate generator f xx /2 asck, asck2 selector internal bus
37 m pd784031y (2) 3-wire serial i/o mode in this mode, the master device starts transfer by making the serial clock active and transfers 1-byte data in synchronization with this clock. this mode is used to communicate with a device having the conventional clocked serial interface. basically, communication is established by using three lines: one serial clock (sck) and two serial data (si and so) lines. generally, to check the communication status, a handshake line is necessary. figure 7-11. block diagram in 3-wire serial i/o mode remark f xx : oscillation frequency or external clock input n = 0 through 11 m = 1 or 16 through 30 internal bus direction control circuit sio1, sio2 shift register output latch serial clock counter serial clock control circuit interrupt signal generation circuit 1/m 1/2 n + 1 intcsi1, intcsi2 si1, si2 so1, so2 sck1, sck2 f xx /2 selector
38 m pd784031y 7.8.2 clocked serial interface (csi) in this mode, the master device starts transfer by making the serial clock active and communicates 1-byte data in synchronization with this clock. figure 7-12. block diagram of clocked serial interface remark f xx : oscillation frequency or external clock input internal bus direction control register slave address register selector selector selector acknowledge detection control wake-up control circuit prescaler shift register output latch match signal set reset si0 so0/sda n-ch open drain output (in 2-wire or i 2 c bus mode) stop condition detection circuit serial clock counter sck0/scl serial clock control circuit n-ch open drain output (in 2-wire or i 2 c bus mode) cls0 cls1 timer 3 output f xx /16 f xx /2 interrupt signal generation circuit intcsi intspc start condition detection circuit acknowledge detection circuit
39 m pd784031y (1) 3-wire serial i/o mode this mode is to communicate with devices having the conventional clocked serial interface. basically, communication is established in this mode with three lines: one serial clock (sck0) and two serial data (si0 and so0) lines. generally, a handshake line is necessary to check the communication status. (2) 2-wire serial i/o mode this mode is to transfer 8-bit data by using two lines: serial clock (scl) and serial data bus (sda). generally, a handshake line is necessary to check the communication status. (3) i 2 c (inter ic) bus mode this mode is to communicate with devices conforming to the i 2 c bus format. this mode is to transfer 8-bit data with two or more devices by using two lines: serial clock (scl) and serial data bus (sda). during transfer, a start condition, data, and stop condition can be output onto the serial data bus. during reception, these data can be automatically detected by hardware. 7.9 edge detection function the interrupt input pins (nmi and intp0 through intp5) are used not only to input interrupt requests but also to input trigger signals to the internal hardware units. because these pins operate at an edge of the input signal, they have a functio n to detect an edge. moreover, a noise reduction circuit is also provided to prevent erroneous detection due to noise. pin name detectable edge noise reduction nmi either of rising or falling edge by analog delay intp0 to intp3 either or both of rising and falling edges by clock sampling note intp4, intp5 by analog delay note intp0 can select a sampling clock.
40 m pd784031y 7.10 watchdog timer a watchdog timer is provided to detect a hang up of the cpu. this watchdog timer generates a non-maskable interrupt unless it is cleared by software within a specified interval time. once enabled to operate, the watchdog timer cannot be stopped by software. whether the interrupt by the watchdog timer or the interrupt input from the nmi pin takes precedence can be specified. figure 7-13. block diagram of watchdog timer selector f clk /2 21 f clk /2 20 f clk /2 19 f clk /2 17 f clk clear signal timer intwdt
41 m pd784031y 8. interrupt function as the servicing in response to an interrupt request, the three types shown in table 8-1 can be selected by program. table 8-1. servicing of interrupt request servicing mode entity of servicing servicing contents of pc and psw vector interrupt software branches and executes servicing routine saves to and restores (servicing is arbitrary). from stack. context switching automatically switches register bank, saves to or restores from branches and executes servicing routine fixed area in register bank. (servicing is arbitrary). macro service firmware executes data transfer between memory retained and i/o (servicing is fixed). 8.1 interrupt sources table 8-2 shows the interrupt sources available. as shown, interrupts are generated by 24 types of sources, execution of the brk instruction or brkcs instruction, or an operand error. the priority of interrupt servicing can be set to four levels, so that nesting can be controlled during interrupt servicing and that which of the two or more interrupts that simultaneously occur should be serviced first. when the macro service function is used, however, nesting always proceeds. the default priority is the priority (fixed) of the service that is performed if two or more interrupt requests, having the sam e request, simultaneously generate (refer to table 8-2 ).
42 m pd784031y table 8-2. interrupt sources type default source internal/ macro service priority name trigger external software C brk instruction instruction execution C C brkcs instruction operand error if result of exclusive or between byte of operand and byte is not ffh when mov stbc, #byte, mov wdm, #byte, or location instruction is executed non-maskable C nmi detection of pin input edge external C wdt overflow of watchdog timer internal maskable 0 (highest) intp0 detection of pin input edge external ? (tm1/tm1w capture trigger, tm1/tm1w event counter input) 1 intp1 detection of pin input edge (tm2/tm2w capture trigger, tm2/tm2w event counter input) 2 intp2 detection of pin input edge (tm2/tm2w capture trigger, tm2/tm2w event counter input) 3 intp3 detection of pin input edge (tm0 capture trigger, tm0 event counter input) 4 intc00 generation of tm0-cr00 match signal internal ? 5 intc01 generation of tm0-cr01 match signal 6 intc10 generation of tm1-cr10 match signal (in 8-bit operation mode) generation of tm1w-cr10w match signal (in 16-bit operation mode) 7 intc11 generation of tm1-cr11 match signal (in 8-bit operation mode) generation of tm1w-cr11w match signal (in 16-bit operation mode) 8 intc20 generation of tm2-cr20 match signal (in 8-bit operation mode) generation of tm2w-cr20w match signal (in 16-bit operation mode) 9 intc21 generation of tm2-cr21 match signal (in 8-bit operation mode) generation of tm2w-cr21w match signal (in 16-bit operation mode) 10 intc30 generation of tm3-cr30 match signal (in 8-bit operation mode) generation of tm3w-cr30w match signal (in 16-bit operation mode) 11 intp4 detection of pin input edge external ? 12 intp5 detection of pin input edge 13 intad end of a/d conversion (transfer of adcr) internal ? 14 intser occurrence of asi0 reception error C 15 intsr end of asi0 reception or csi1 transfer ? intcsi1 16 intst end of asi0 transfer 17 intcsi end of csi1 transfer 18 intser2 occurrence of asi2 reception error C 19 intsr2 end of asi2 reception or csi2 transfer ? intcsi2 20 intst2 end of asi2 transfer 21 (lowest) intspc i 2 c bus stop condition interrupt remark asi: asynchronous serial interface csi: clocked serial interface
43 m pd784031y 8.2 vectored interrupt execution branches to a servicing routing by using the memory contents of a vector table address corresponding to the interrupt source as the address of the branch destination. so that the cpu performs interrupt servicing, the following operations are performed: ? on branching : saves the status of the cpu (contents of pc and psw) to stack ? on returning : restores the status of the cpu (contents of pc and psw) from stack to return to the main routine from an interrupt service routine, the reti instruction is used. the branch destination address is in a range of 0 to ffffh. table 8-3. vector table address interrupt source vector table address brk instruction 003eh operand error 003ch nmi 0002h wdt 0004h intp0 0006h intp1 0008h intp2 000ah intp3 000ch intc00 000eh intc01 0010h intc10 0012h intc11 0014h intc20 0016h intc21 0018h intc30 001ah intp4 001ch intp5 001eh intad 0020h intser 0022h intsr 0024h intcsi1 intst 0026h intcsi 0028h intser2 002ah intsr2 002ch intcsi2 intst2 002eh intspc 0030h
44 m pd784031y 8.3 context switching when an interrupt request is generated or when the brkcs instruction is executed, a predetermined register bank is selected by hardware. context switching is a function that branches execution to a vector address stored in advance in the register bank, and to stack the current contents of the program counter (pc) and program status word (psw) to the register bank. the branch address is in a range of 0 to ffffh. figure 8-1. context switching operation when interrupt request is generated 8.4 macro service this function is to transfer data between memory and a special function register (sfr) without intervention by the cpu. a macro service controller accesses the memory and sfr in the same transfer cycle and directly transfers data without loading it. because this function does not save or restore the status of the cpu, or load data, data can be transferred at high speeds. figure 8-2. macro service cpu memory sfr macro service controller read write write read internal bus register bank n (n = 0 to 7) 0000b <7> transfer pc19 to 16 pc15 to 0 <6> exchange <5> save <2> save temporary register <1> save psw v u t w a b r5 r7 d h x c r4 r6 e l vp up <3> switching of register bank (rbs0 to rbs2 ? n) register bank n (0 to 7) (bits 8 through 11 of temporary register) <4> rss ? 0 ie ? 0
45 m pd784031y 8.5 application example of macro service (1) transfer of serial interface each time macro service request intst is generated, the next transfer data is transferred from memory to txs. when data n (last byte) has been transferred to txs (when the transfer data storage buffer has become empty), vectored interrupt request intst is generated. (2) reception of serial interface each time macro service request intsr is generated, the receive data is transferred from rxb to memory. when data n (last byte) has been transferred to memory (when the receive data storage buffer has become full), vectored interrupt request intsr is generated. receive data storage buffer (memory) data n data n 1 data 1 data 2 internal bus receive shift register rxb (sfr) reception control intsr rxd receive buffer transfer data storage buffer (memory) data n data n 1 data 1 data 2 internal bus transfer shift register txs (sfr) transfer control intst txd
46 m pd784031y (3) real-time output port intc10 and intc11 serve as the output triggers of the real-time output port. the macro services for these can set the following output pattern and intervals simultaneously. therefore, intc10 and intc11 can control two stepping motors independently of each other. they can also be used for pwm output or to control dc motors. each time macro service request intc10 is generated, the pattern and timing are transferred to the buffer register (p0l) and compare register (cr10), respectively. when the contents of the timer register 1 (tm1) coincide with those of cr10, intc10 is generated again, and the contents of p0l are transferred to the output latch. when tn (last byte) has transferred to cr10, vectored interrupt request intc10 is generated. the same applies to intc11. output timing profile (memory) t n t n 1 t 1 t 2 internal bus cr10 (sfr) tm1 intc10 output pattern profile (memory) p n p n 1 p 1 p 2 internal bus p0l output latch (sfr) match p00 to p03
47 m pd784031y 9. local bus interface the local bus interface can connect an external memory or i/o (memory mapped i/o) and support a memory space of 1 mbytes (refer to figure 9-1 ). figure 9-1. example of local bus interface 9.1 memory expansion the memory capacity can be expanded in seven steps, from 256 bytes to 1 mbytes, by connecting an external program memory and data memory. decoder latch pseudo sram prom pd27c1001a character generator pd24c1000 data bus address bus gate array i/o expansion centronics i/f, etc. pd784031y a16 to a19 rd wr refrq ad0 to ad7 astb a8 to a15 m m m
48 m pd784031y 9.2 memory space the 1-mbyte memory space is divided into eight spaces of logical addresses. each space can be controlled by using the programmable wait function and pseudo static ram refresh function. figure 9-2. memory space 512 kbytes 256 kbytes 128 kbytes 64 kbytes 16 kbytes 16 kbytes 16 kbytes 16 kbytes h f f f f f h 0 0 0 0 8 h f f f f 7 h 0 0 0 0 4 h f f f f 3 h 0 0 0 0 2 h f f f f 1 h 0 0 0 0 0 h f f f 3 0 h 0 0 0 4 0 h f f f 7 0 h 0 0 0 8 0 h f f f b 0 h 0 0 0 c 0 h f f f f 0 h 0 0 0 0 1
49 m pd784031y 9.3 programmable wait the memory space can be divided into eight spaces and wait states can be independently inserted in each of these spaces while the rd and wr signals are active. even when a memory with a different access time is connected, therefore, the efficiency of the entire system does not drop. in addition, an address wait function that extends the active period of the astb signal is also provided so as to have a sufficient address decode time (this function can be set to the entire space). 9.4 pseudo static ram refresh function the following refresh operations can be performed: ? pulse refresh : a bus cycle that outputs a refresh pulse to the refrq pin at a fixed cycle is inserted. the memory spaces is divided into eight spaces, and a refresh pulse can be output from the refrq pin while a specified memory space is accessed. therefore, the normal memory access is not kept to wait by the refresh cycle. ? power-down self-refresh : the low level is output to the refrq pin in the standby mode to retain the contents of the pseudo static ram. 9.5 bus hold function a bus hold function is provided to facilitate connection of a dma controller. when a bus hold request signal (hldrq) is received from an external bus master, the address bus, address/data bus, and astb, rd, and wr pins go into a high- impedance state when the current bus cycle has been completed. this makes the bus hold acknowledge (hldak) signal active, and releases the bus to the external bus master. note that, while the bus hold function is used, the external wait function and pseudo static ram refresh function cannot be used.
50 m pd784031y 10. standby function this function is to reduce the power dissipation of the chip, and can be used in the following modes: ? halt mode : stops supply of the operating clock to the cpu. this mode is used in combination with the normal operation mode for intermittent operation to reduce the average power dissipation. ? idle mode : stops the entire system with the oscillation circuit continuing operation. the power dissipation in this mode is close to that in the stop mode. however, the time required to restore the normal program operation from this mode is almost the same as that from the halt mode. ? stop mode : stops the oscillator and thereby to stop all the internal operations of the chip. consequently, the power dissipation is minimized with only leakage current flowing. these modes are programmable. the macro service can be started from the halt mode. figure 10-1. transition of standby status waits for oscillation stabilization program operation macro service halt (standby) idle (standby) stop (standby) oscillation stabilization time expires macro service request end of one processing end of macro service macro service request end of one processing interrupt request note 2 reset input sets halt mode interrupt request of masked interrupt sets idle mode reset input nmi, intp4, intp5 input note 1 sets stop mode reset input nmi, intp4, intp5 input note 1 notes 1. when intp4 and intp5 are not masked 2. only interrupt requests that are not masked remark only the externally input nmi is valid. the watchdog timer cannot be used to release the standby mode (stop/ idle mode).
51 m pd784031y 11. reset function when the low level is input to the reset pin, the internal hardware is initialized (reset status). when the reset pin goes high, the following data are set to the program counter (pc). ? lower 8 bits of pc : contents of address 0000h ? middle 8 bits of pc : contents of address 0001h ? higher 4 bits of pc : 0 program execution is started from a branch destination address which is the contents of the pc. therefore, the system can be reset and started from any address. set the contents of each register by program as necessary. the reset input circuit has a noise reduction circuit to prevent malfunctioning due to noise. this noise reduction circuit is a sampling circuit by analog delay. figure 11-1. accepting reset signal assert the reset signal active until the oscillation stabilization time (approx. 40 ms) elapses to execute a power-on reset operation. figure 11-2. power-on reset operation delay reset (input) delay internal reset signal reset starts reset ends delay initialize pc executes instruction at reset start address reset (input) internal reset signal reset ends oscillation stabilization time delay initialize pc executes instruction at reset start address v dd
52 m pd784031y 12. instruction set (1) 8-bit instructions (the instructions in parentheses are combinations realized by describing a as r) mov, xch, add, addc, sub, subc, and, or, xor, cmp, mulu, divuw, inc, dec, ror, rol, rorc, rolc, shr, shl, ror4, dbnz, push, pop, movm, xchm, cmpme, cmpmne, cmpmnc, cmpmc, movbk, xchbk, cmpbke, cmpbkne, cmpbknc, cmpbkc, chikl, chkla table 12-1. instruction list by 8-bit addressing second operand #byte a r saddr sfr !addr16 mem r3 [whl+] n none note 2 r' saddr' !!addr24 [saddrp] pswl [whlC] first operand [%saddrg] pswh a (mov) (mov) mov (mov) note 6 mov (mov) mov mov (mov) add note 1 (xch) xch (xch) note 6 (xch) (xch) xch (xch) (add) note 1 (add) note 1 (add) note 1,6 (add) note 1 add note 1 add note 1 (add) note 1 r mov (mov) mov mov mov mov ror note 3 mulu add note 1 (xch) xch xch xch xch divuw (add) note 1 add note 1 add note 1 add note 1 inc dec saddr mov (mov) note 6 mov mov inc add note 1 (add) note 1 add note 1 xch dec add note 1 dbnz sfr mov mov mov push add note 1 (add) note 1 add note 1 pop chkl chkla !addr16 mov (mov) mov !!addr24 add note 1 mem mov [saddrp] add note 1 [%saddrg] mem3 ror4 rol4 r3 mov mov pswl pswh b, c dbnz stbc, wdm mov [tde+] (mov) movbk note 5 [tdeC] (add) note 1 movm note 4 notes 1. the operands of addc, sub, subc, and, or, xor, and cmp are the same as that of add. 2. either the second operand is not used, or the second operand is not an operand address. 3. the operands of rol, rorc, rolc, shr, and shl are the same as that of ror. 4. the operands of xchm, cmpme, cmpmne, cmpmnc, and cmpmc are the same as that of movm. 5. the operands of xchbk, cmpbke, cmpbkne, cmpbknc, and cmpbkc are the same as that of movbk. 6. the code length of some instructions having saddr2 as saddr in this combination is short.
53 m pd784031y (2) 16-bit instructions (the instructions in parentheses are combinations realized by describing ax as rp) movw, xchw, addw, subw, cmpw, muluw, mulw, divux, incw, decw, shrw, shlw, push, pop, addwg, subwg, pushu, popu, movtblw, macw, macsw, sacw table 12-2. instruction list by 16-bit addressing second operand #word ax rp saddrp sfrp !addr16 mem [whl+] byte n none note 2 rp' saddrp' !!addr24 [saddrp] first operand [%saddrg] ax (movw) (movw) (movw) (movw) note 3 movw (movw) movw (movw) addw note 1 (xchw) (xchw) (xchw) note 3 (xchw) xchw xchw (xchw) (add) note 1 (addw) note 1 (addw) note 1,3 (addw) note 1 rp movw (movw) movw movw movw movw shrw mulw note 4 addw note 1 (xchw) xchw xchw xchw shlw incw (addw) note 1 addw note 1 addw note 1 addw note 1 decw saddrp movw (movw) note 3 movw movw incw addw note 1 (addw) note 1 addw note 1 xchw decw addw note 1 sfrp movw movw movw push addw note 1 (addw) note 1 addw note 1 pop !addr16 movw (movw) movw movtblw !!addr24 mem movw [saddrp] [%saddrg] psw push pop sp addwg subwg post push pop pushu popu [tde+] (movw) sacw byte macw macsw notes 1. the operands of subw and cmpw are the same as that of addw. 2. either the second operand is not used, or the second operand is not an operand address. 3. the code length of some instructions having saddrp2 as saddrp in this combination is short. 4. the operands of muluw and divux are the same as that of mulw.
54 m pd784031y (3) 24-bit instructions (the instructions in parentheses are combinations realized by describing whl as rg) movg, addg, subg, incg, decg, push, pop table 12-3. instruction list by 24-bit addressing second operand #imm24 whl rg saddrg !!addr24 mem1 [%saddrg] sp none note rg' first operand whl (movg) (movg) (movg) (movg) (movg) movg movg movg (addg) (addg) (addg) addg (subg) (subg) (subg) subg rg movg (movg) movg movg movg incg addg (addg) addg decg subg (subg) subg push pop saddrg (movg) movg !!addr24 (movg) movg mem1 movg [%saddrg] movg sp movg movg incg decg note either the second operand is not used, or the second operand is not an operand address.
55 m pd784031y (4) bit manipulation instructions mov1, and1, or1, xor1, set1, clr1, not1, bt, bf, btclr, bfset table 12-4. bit manipulation instructions second operand cy saddr.bit sfr.bit /saddr.bit /sfr. bit none note a.bit x.bit /a.bit /x.bit pswl.bit pswh.bit /pswl.bit /pswh.bit mem2.bit /mem2.bit first operand !addr16.bit !!addr24.bit /!addr16.bit /!!addr24.bit cy mov1 and1 not1 and1 or1 set1 or1 clr1 xor1 saddr.bit mov1 not1 sfr.bit set1 a.bit clr1 x.bit bf pswl.bit bt pswh.bit btclr mem2.bit bfset !addr16.bit !!addr24.bit note either the second operand is not used, or the second operand is not an operand address.
56 m pd784031y (5) call and return/branch instructions call, callf, callt, brk, ret, reti, retb, retcs, retcsb, brkcs, br, bnz, bne, bz, be, bnc, bnl, bc, bl, bnv, bpo, bv, bpe, bp, bn, blt, bge, ble, bgt, bnh, bh, bf, bt, btclr, bfset, dbnz table 12-5. call and return/branch instructions operand of instruction $addr20 $!addr20 !addr16 !!addr20 rp rg [rp] [rg] !addr11 [addr5] rbn none address basic instruction bc note call call call call call call call callf callf brkcs brk br br br br br br br br ret retcs reti retcsb retb compound instruction bf bt btclr bfset dbnz note the operands of bnz, bne, bz, be, bnc, bnl, bl, bnv, bpo, bv, bpe, bp, bn, blt, bge, ble, bgt, bnh, and bh are the same as bc. (6) other instructions adjba, adjbs, cvtbw, location, sel, not, ei, di, swrs
57 m pd784031y 13. electrical specifications absolute maximum ratings (t a = 25 c) parameter symbol test conditions ratings unit supply voltage v dd C0.5 to +7.0 v av dd av ss to v dd + 0.5 v av ss C0.5 to +0.5 v input voltage v i C0.5 to v dd + 0.5 v output voltage v o C0.5 to v dd + 0.5 v output current low-level i ol 1 pin 15 ma total of output pins 100 ma output current high-level i oh 1 pin C10 ma total of output pins C100 ma reference input voltage av ref1 C0.5 to v dd + 0.3 v to a/d converter reference input voltage av ref2 C0.5 to v dd + 0.3 v to d/a converter av ref3 C0.5 to v dd + 0.3 v operating ambient t a C40 to +85 c temperature storage temperature t stg C65 to +150 c caution the product quality may be damaged even if a value of only one of the above parameters exceeds the absolute maximum rating or any value exceeds the absolute maximum rating for an instant. that is, the absolute maximum rating is a rating value which may cause a product to be damaged physically. the absolute maximum rating values must therefore be observed in using the product.
58 m pd784031y operating condition ? operating ambient temperature (t a ) : C40 to +85 c ? rise, fall time (t r , t f ) (unspecified pins) : 0 to 200 m s ? supply voltage and clock cycle time : refer to figure 13-1 figure 13-1. supply voltage and clock cycle time capacitance (t a = 25 c, v dd = v ss = 0 v) parameter symbol test conditions min. typ. max. unit input capacitance c i f = 1 mhz 10 pf output capacitance c o unmeasured pins returned to 10 pf i/o capacitance c io 0 v. 10 pf 10000 4000 1000 125 100 62.5 10 01234567 guaranteed operation range supply voltage [v] clock cycle time t cyk [ns]
59 m pd784031y oscillator characteristics (t a = e40 to +85 c, v dd = +4.5 to 5.5 v, v ss = 0 v) resonator recommended circuit parameter min. max. unit ceramic resonator or oscillation frequency (f xx ) 4 32 mhz crystal resonator external clock x1 input frequency (f x ) 4 32 mhz x1 input rise, fall time (t xr , t xf ) 0 10 ns x1 input high-/low-level width 10 125 ns (t wxh , t wxl ) caution when using the clock oscillator, wiring in the area enclosed with the dotted line should be carried out as follows to avoid an adverse effect from wiring capacitance. ? wiring should be as short as possible. ? wiring should not cross other signal lines. ? wiring should not be placed close to a varying high current. ? the potential of the oscillator capacitor ground should be the same as v ss1 . do not ground it to the ground pattern in which a high current flows. ? do not fetch a signal from the oscillator. v ss1 x1 x2 c2 c1 x1 x2 hcmos inverter
60 m pd784031y oscillator characteristics (t a = e40 to +85 c, v dd = +2.7 to 5.5 v, v ss = 0 v) resonator recommended circuit parameter min. max. unit ceramic resonator or oscillation frequency (f xx ) 4 16 mhz crystal resonator external clock x1 input frequency (f x ) 4 16 mhz x1 input rise, fall time (t xr , t xf ) 0 10 ns x1 input high-/low-level width 10 125 ns (t wxh , t wxl ) caution when using the clock oscillator, wiring in the area enclosed with the dotted line should be carried out as follows to avoid an adverse effect from wiring capacitance. ? wiring should be as short as possible. ? wiring should not cross other signal lines. ? wiring should not be placed close to a varying high current. ? the potential of the oscillator capacitor ground should be the same as v ss1 . do not ground it to the ground pattern in which a high current flows. ? do not fetch a signal from the oscillator. v ss1 x1 x2 c2 c1 x1 x2 hcmos inverter
61 m pd784031y dc characteristics (t a = e40 to +85 c, v dd = av dd = +2.7 to 5.5 v, v ss = av ss = 0 v) (1/2) parameter symbol test conditions min. typ. max. unit input voltage low-level v il1 except for pins shown in C0.3 0.3v dd v notes 1, 2, 3, 4, 6 v il2 pins shown in notes 1, 2, 3, 4, 6 C0.3 0.2v dd v v il3 v dd = +5.0 v 10 % C0.3 +0.8 v pins shown in notes 2, 3, 4 input voltage high-level v ih1 except for pins shown in notes 1, 6 0.7v dd v dd + 0.3 v v ih2 pins shown in notes 1, 6 0.8v dd v dd + 0.3 v v ih3 v dd = +5.0 v 10 % 2.2 v dd + 0.3 v pins shown in notes 2, 3, 4 output voltage low-level v ol1 i ol = 2 ma 0.4 v except for pins shown in note 6 v ol2 i ol = 3 ma 0.4 v pins shown in note 6 i ol = 6 ma 0.6 v pins shown in note 6 v ol3 v dd = +5.0 v 10 % 1.0 v i ol = 8 ma pins shown in notes 2, 5 output voltage high-level v oh1 i oh = C2 ma v dd C 1.0 v v oh2 v dd = +5.0 v 10 % v dd C 1.4 v i oh = C5 ma pins shown in note 4 x1 input current low-level i il extc = 0 C30 m a 0 v v i v il2 x1 input current high-level i ih extc = 0 +30 m a v ih2 v i v dd notes 1. x1, x2, reset, p12/asck2/sck2, p20/nmi, p21/intp0, p22/intp1, p23/intp2/ci, p24/intp3, p25/intp4/asck/sck1, p26/intp5, p27/si0, test 2. ad0 to ad7, a8 to a15 3. p60/a16 to p63/a19, rd, wr, p66/wait/hldrq, p67/refrq/hldak 4. p00 to p07 5. p10 to p17 6. p32/sck0/scl, p33/so0/sda
62 m pd784031y dc characteristics (t a = e40 to +85 c, v dd = av dd = +2.7 to 5.5 v, v ss = av ss = 0 v) (2/2) parameter symbol test conditions min. typ. max. unit input leakage current i li 0 v v i v dd 10 m a except for x1 pin when extc = 0 output leakage current i lo 0 v v o v dd 10 m a v dd supply current i dd1 operating f xx = 32 mhz 25 45 ma mode v dd = +5.0 v 10 % f xx = 16 mhz 12 25 ma v dd = +2.7 to 3.3 v i dd2 halt mode f xx = 32 mhz 13 26 ma v dd = +5.0 v 10 % f xx = 16 mhz 8 12 ma v dd = +2.7 to 3.3 v i dd3 idle mode f xx = 32 mhz 12 ma (extc = 0) v dd = +5.0 v 10 % f xx = 16 mhz 8 ma v dd = +2.7 to 3.3 v pull-up resistor r l v i = 0 v 15 80 k w
63 m pd784031y ac characteristics (t a = e40 to +85 c, v dd = av dd = +2.7 to 5.5 v, v ss = av ss = 0 v) (1) read/write operation (1/2) parameter symbol test conditions min. max. unit address setup time t sast v dd = +5.0 v 10 % (0.5 + a) t C 15 ns (0.5 + a) t C 31 ns astb high-level width t wsth v dd = +5.0 v 10 % (0.5 + a) t C 17 ns (0.5 + a) t C 40 ns address hold time (from astb )t hstla v dd = +5.0 v 10 % 0.5t C 24 ns 0.5t C 34 ns address hold time (from rd - )t hra 0.5t C 14 ns address ? rd delay time t dar v dd = +5.0 v 10 % (1 + a) t C 9 ns (1 + a) t C 15 ns address float time (from rd )t fra 0ns address ? data input time t daid v dd = +5.0 v 10 % (2.5 + a + n) t C 37 ns (2.5 + a + n) t C 52 ns astb ? data input time t dstid v dd = +5.0 v 10 % (2 + n) t C 40 ns (2 + n) t C 60 ns rd ? data input time t drid v dd = +5.0 v 10 % (1.5 + n) t C 50 ns (1.5 + n) t C 70 ns astb ? rd delay time t dstr 0.5t C 9 ns data hold time (from rd - )t hrid 0ns rd - ? address active time t dra after program v dd = +5.0 v 10 % 0.5t C 8 ns read 0.5t C 12 ns after data v dd = +5.0 v 10 % 1.5t C 8 ns read 1.5t C 12 ns rd - ? astb - delay time t drst 0.5t C 17 ns rd low-level width t wrl v dd = +5.0 v 10 % (1.5 + n) t C 30 ns (1.5 + n) t C 40 ns address hold time (from wr - )t hwa 0.5t C 14 ns address ? wr delay time t daw v dd = +5.0 v 10 % (1 + a) t C 5 ns (1 + a) t C 15 ns astb ? data output delay time t dstod v dd = +5.0 v 10 % 0.5t + 19 ns 0.5t + 35 ns wr ? data output delay time t dwod 0.5t C 11 ns astb ? wr output delay time t dstw 0.5t C 9 ns remark t: t cyk (system clock cycle time) a : 1 in address wait, 0 in the other conditions n : the number of wait (n 3 0)
64 m pd784031y (1) read/write operation (2/2) parameter symbol test conditions min. max. unit data setup time (to wr - )t sodw v dd = +5.0 v 10 % (1.5 + n) t C 30 ns (1.5 + n) t C 40 ns data hold time (from wr - ) note t hwod v dd = +5.0 v 10 % 0.5t C 5 ns 0.5t C 25 ns wr - ? astb - delay time t dwst 0.5t C 12 ns wr low-level width t wwl v dd = +5.0 v 10 % (1.5 + n) t C 30 ns (1.5 + n) t C 40 ns note the data hold time includes the time to hold v oh1 and v ol1 in the load condition of c l = 50 pf, r l = 4.7 k w . remark t: t cyk (system clock cycle time) n : the number of wait (n 3 0) (2) bus hold timing parameter symbol test conditions min. max. unit hldrq - ? float delay time t fhqc (6 + a + n) t + 50 ns hldrq - ? hldak - t dhqhhah v dd = +5.0 v 10 % (7 + a + n) t + 30 ns delay time (7 + a + n) t + 40 ns float ? hldak - delay time t dcfha 1t + 30 ns hldrq ? hldak t dhqlhal v dd = +5.0 v 10 % 2t + 40 ns delay time 2t + 60 ns hldak ? active delay time t dhac v dd = +5.0 v 10 % 1t C 20 ns 1t C 30 ns remark t: t cyk (system clock cycle time) a : 1 in address wait, 0 in the other conditions n : the number of wait (n 3 0)
65 m pd784031y (3) external wait timing parameter symbol test conditions min. max. unit address ? wait input time t dawt v dd = +5.0 v 10 % (2 + a) t C 40 ns (2 + a) t C 60 ns astb ? wait input time t dstwt v dd = +5.0 v 10 % 1.5t C 40 ns 1.5t C 60 ns astb ? wait hold time t hstwth v dd = +5.0 v 10 % (0.5 + n) t + 5 ns (0.5 + n) t + 10 ns astb ? wait - delay time t dstwth v dd = +5.0 v 10 % (1.5 + n) t C 40 ns (1.5 + n) t C 60 ns rd ? wait input time t drwtl v dd = +5.0 v 10 % t C 50 ns t C 70 ns rd ? wait hold time t hrwt v dd = +5.0 v 10 % nt + 5 ns nt + 10 ns rd ? wait - delay time t drwth v dd = +5.0 v 10 % (1 + n) t C 40 ns (1 + n) t C 60 ns wait - ? data input time t dwtid v dd = +5.0 v 10 % 0.5t C 5 ns 0.5t C 10 ns wait - ? wr - delay time t dwtw 0.5t ns wait - ? rd - delay time t dwtr 0.5t ns wr ? wait input time t dwwtl v dd = +5.0 v 10 % t C 50 ns t C 75 ns wr ? wait hold time t hwwt v dd = +5.0 v 10 % nt + 5 ns nt + 10 ns wr ? wait - delay time t dwwth v dd = +5.0 v 10 % (1 + n) t C 40 ns (1 + n) t C 70 ns remark t: t cyk (system clock cycle time) a : 1 in address wait, 0 in the other conditions n : the number of wait (n 3 0) (4) refresh timing parameter symbol test conditions min. max. unit random read/write cycle time t rc 3t ns refrq low-level pulse width t wrfql v dd = +5.0 v 10 % 1.5t C 25 ns 1.5t C 30 ns astb ? refrq delay time t dstrfq 0.5t C 9 ns rd - ? refrq delay time t drrfq 1.5t C 9 ns wr - ? refrq delay time t dwrfq 1.5t C 9 ns refrq - ? astb delay time t drfqst 0.5t C 15 ns refrq high-level pulse width t wrfqh v dd = +5.0 v 10 % 1.5t C 25 ns 1.5t C 30 ns remark t: t cyk (system clock cycle time)
66 m pd784031y serial operation (t a = e40 to +85 c, v dd = +2.7 to 5.5 v, av ss = v ss = 0 v) (1) csi parameter symbol test conditions min. max. unit serial clock cycle time (sck0) t cysk0 input external clock 10/f xx + 380 ns when sck0, so0 are cmos input/output output t m s serial clock low-level width t wskl0 input external clock 5/f xx + 150 ns (sck0) when sck0, so0 are cmos input/output output 0.5t C 40 m s serial clock high-level width t wskh0 input external clock 5/f xx + 150 ns (sck0) when sck0, so0 are cmos input/output output 0.5t C 40 m s si0 setup time (to sck0 - )t sssk0 40 ns si0 hold time (from sck0 - )t hssk0 5/f xx + 40 ns so0 output delay time t dsbsk1 cmos push-pull output 0 5/f xx + 150 ns (from sck0 ) (3-wire serial i/o mode) t dsbsk2 open drain output 0 5/f xx + 400 ns (2-wire serial i/o mode), r l = 1 k w remarks 1. the values shown in the table above are those in the condition of c l = 100 pf. 2. t : serial clock cycle set by the software. the minimum value is 16/f xx . 3. f xx : oscillation frequency (2) i 2 c parameter symbol standard mode i 2 c bus high-speed mode i 2 c bus unit f xx = 4 to 32 mhz f xx = 8 to 32 mhz min. max. min. max. scl clock frequency f scl 0 100 0 400 khz low status hold time of scl t low 4.7 1.3 m s clock high status hold time of scl t high 4.0 0.6 m s clock data hold time t hd ; dat 300 300 900 ns data setup time t su ; dat 250 100 ns sda, scl signal rise time t r 1000 20 + 0.1cb 300 ns sda, scl signal fall time t f 300 20 + 0.1cb 300 ns load capacitance of each bus line cb 400 400 pf
67 m pd784031y (3) ioe1, ioe2 parameter symbol test conditions min. max. unit serial clock cycle time t cysk1 input v dd = +5.0 v 10 % 250 ns (sck1, sck2) 500 ns output internal 16 frequency division t ns serial clock low-level width t wskl1 input v dd = +5.0 v 10 % 85 ns (sck1, sck2) 210 ns output internal 16 frequency division 0.5t C 40 ns serial clock high-level width t wskh1 input v dd = +5.0 v 10 % 85 ns (sck1, sck2) 210 ns output internal 16 frequency division 0.5t C 40 ns si1, si2 setup time t sssk1 40 ns (to sck1, sck2 - ) si1, si2 hold time t hssk1 40 ns (from sck1, sck2 - ) so1, so2 output delay time t dsosk 050ns (from sck1, sck2 ) so1, so2 output hold time t hsosk when transferring data 0.5t cysk1 C 40 ns (from sck1, sck2 - ) remarks 1. the values shown in the table above are those in the condition of c l = 100 pf. 2. t: serial clock cycle set by the software. the minimum value is 16/f xx . (4) uart, uart2 parameter symbol test conditions min. max. unit asck clock input cycle time t cyask v dd = +5.0 v 10 % 125 ns 250 ns asck clock low-level width t waskl v dd = +5.0 v 10 % 52.5 ns 85 ns asck clock high-level width t waskh v dd = +5.0 v 10 % 52.5 ns 85 ns
68 m pd784031y other operations parameter symbol test conditions min. max. unit nmi low-level width t wnil 10 m s nmi high-level width t wnih 10 m s intp0 low-level width t wit0l 3t cysmp + 10 ns intp0 high-level width t wit0h 3t cysmp + 10 ns intp1 to intp3, ci low-level width t wit1l 3t cycpu + 10 ns intp1 to intp3, ci high-level width t wit1h 3t cycpu + 10 ns intp4, intp5 low-level width t wit2l 10 m s intp4, intp5 high-level width t wit2h 10 m s reset low-level width t wrsl 10 m s reset high-level width t wrsh 10 m s remark t cysmp : sampling clock set by the software t cycpu : cpu operation clock set by the software a/d converter characteristics (t a = C40 to +85 c, v dd = av dd = av ref1 = +2.7 to 5.5 v, v ss = av ss = 0 v) parameter symbol test conditions min. typ. max. unit resolution 8 bit total error note 1.0 % linearity error note 0.8 % quantization error 1/2 lsb conversion time t conv fr = 1 120 t cyk fr = 0 180 t cyk sampling time t samp fr = 1 24 t cyk fr = 0 36 t cyk analog input voltage v ian C0.3 av ref1 + 0.3 v analog input impedance r an 1000 m w av ref1 current ai ref1 0.5 1.5 ma av dd supply current ai dd1 f xx = 32 mhz, cs = 1 2.0 5.0 ma ai dd2 stop mode, cs = 0 1.0 20 m a note quantization error is not included. this is expressed in proportion to the full-scale value. remark t cyk : system clock cycle time
69 m pd784031y d/a converter characteristics (t a = e40 to +85 c, v dd = av dd = +2.7 to 5.5 v, v ss = av ss = 0 v) parameter symbol test conditions min. typ. max. unit resolution 8 bit total error load v dd = av dd = av ref2 0.6 % condition = +2.7 to 5.5 v 4 m w , 30 pf av ref3 = 0 v v dd = av dd = +2.7 to 5.5 v 0.8 % av ref2 = 0.75v dd av ref3 = 0.25v dd load v dd = av dd = av ref2 0.8 % condition = +2.7 to 5.5 v 2 m w , 30 pf av ref3 = 0 v v dd = av dd = +2.7 to 5.5 v 1.0 % av ref2 = 0.75v dd av ref3 = 0.25v dd settling time load condition 2 m w , 30 pf 10 m s output resistance r o dacs0, 1 = 55 h 10 k w analog reference voltage av ref2 0.75v dd v dd v av ref3 0 0.25v dd v av ref2 , av ref3 resistance value r airef dacs0, 1 = 55 h 4 8 k w reference supply input current ai ref2 05ma ai ref3 C5 0 ma
70 m pd784031y data retention characteristics (t a = e40 to +85 c) parameter symbol test conditions min. typ. max. unit data retention voltage v dddr stop mode 2.5 5.5 v data retention current i dddr v dddr = +2.7 to 5.5 v 10 50 m a v dddr = +2.5 v 2 10 m a v dd rise time t rvd 200 m s v dd fall time t fvd 200 m s v dd hold time t hvd 0ms (from setting stop mode) stop release signal input time t drel 0ms oscillation stabilization wait time t wait crystal resonator 30 ms ceramic resonator 5 ms input voltage low-level v il specified pins note 0 0.1v dddr v input voltage high-level v ih 0.9v dddr v dddr v note reset, p20/nmi, p21/intp0, p22/intp1, p23/intp2/ci, p24/intp3, p25/intp4/asck/sck1, p26/intp5, p27/si0, p32/sck0/scl, and p33/so0/sda pins ac timing test point 0.8v dd or 2.2 v 0.8 v 0.8v dd or 2.2 v 0.8 v test points v dd ? v 0.45 v
71 m pd784031y timing waveform (1) read operation (2) write operation astb a8 to a19 ad0 to ad7 rd t wsth t sast t dstid t hstla t drst t fra t drid t dar t wrl t dstr t daid t hra t dra t hrid astb a8 to a19 ad0 to ad7 wr t wsth t sast t hstla t dwst t daw t dstw t hwod t dstod t dwod t sodw t wwl t hwa
72 m pd784031y hold timing external wait signal input timing (1) read operation (2) write operation adtb, a8 to a19, ad0 to ad7, rd, wr hldrq hldak t dhqhhah t fhqc t dcfha t dhac t dhqlhal astb a8 to a19 ad0 to ad7 rd wait t dstwt t hstwth t dstwth t dawt t dwtid t dwtr t drwtl t hrwt t drwth astb a8 to a19 ad0 to ad7 wr wait t dstwt t hstwth t dstwth t dawt t dwtw t dwwtl t hwwt t dwwth
73 m pd784031y refresh timing waveform (1) random read/write cycle (2) when refresh memory access is simultaneous with read, write (3) refresh after read (4) refresh after write astb wr rd t rc t rc t rc t rc t rc t wrfql astb rd, wr refrq t dstrfq t drfqst t wrfqh astb rd refrq t drfqst t drrfq t wrfql astb wr refrq t drfqst t dwrfq t wrfql
74 m pd784031y serial operation (1) csi (2) i 2 c (3) ioe1, ioe2 (4) uart, uart2 sck si so output data input data t sssk0 t hssk0 t dsbsk1 t wskl0 t wskh0 t hsbsk1 t cysk0 scl sda t high t hd ; dat t su ; dat t f t r t low sck si so output data input data t sssk1 t hssk1 t dsosk t hsosk t wskl1 t wskh1 t cysk1 asck, asck2 t waskh t waskl t cyask
75 m pd784031y interrupt input timing reset input timing nmi intp0 ci, intp1 to intp3 intp4, intp5 t wnih t wnil t wit0h t wit0l t wit1h t wit1l t wit2h t wit2l reset t wrsh t wrsl
76 m pd784031y external clock timing data retention characteristics x1 t wxh t wxl t cyx t xf t xr v dd reset nmi (release by falling edge) nmi (release by rising edge) t hvd t fvd t rvd t drel v dddr stop mode setting t wait
77 m pd784031y 14. package drawings remark dimensions and materials of es products are the same as those of mass-produced products. 80 pin plastic qfp (14 14) item millimeters inches note each lead centerline is located within 0.13 mm (0.005 inch) of its true position (t.p.) at maximum material condition. l 0.8?.2 0.031 +0.009 ?.008 m 0.15 0.006 n 0.10 0.004 p 2.7 0.106 a 17.2?.4 0.677?.016 b 14.0?.2 0.551 +0.009 ?.008 c 14.0?.2 0.551 +0.009 ?.008 d 17.2?.4 0.677?.016 f 0.825 0.032 g 0.825 0.032 h 0.30?.10 0.012 +0.004 ?.005 i 0.13 0.005 j 0.65 (t.p.) 0.026 (t.p.) q 0.1?.1 0.004?.004 r5 ? 5 ? +0.10 ?.05 +0.004 ?.003 m m l k j h q p n r detail of lead end i g k 1.6?.2 0.063?.008 60 61 40 80 1 21 20 41 a b cd f s s80gc-65-3b9-4 s 3.0 max. 0.119 max.
78 m pd784031y remark dimensions and materials of es products are the same as those of mass-produced products. 80 pin plastic qfp (14 14) item millimeters inches note each lead centerline is located within 0.13 mm (0.005 inch) of its true position (t.p.) at maximum material condition. p80gc-65-8bt f 0.825 0.032 b 14.00?.20 0.551 +0.009 ?.008 s 1.70 max. 0.067 max. m 0.17 0.007 +0.001 ?.003 +0.03 ?.07 +0.009 ?.008 c 14.00?.20 0.551 +0.009 ?.008 a 17.20?.20 0.677?.008 g 0.825 0.032 h 0.32?.06 0.013 +0.002 ?.003 i 0.13 0.005 j 0.65 (t.p.) 0.026 (t.p.) k 1.60?.20 0.063?.008 l 0.80?.20 0.031 +0.009 ?.008 n 0.10 0.004 p 1.40?.10 0.055?.004 q 0.125?.075 0.005?.003 r3 3 +7 ? +7 ? d 17.20?.20 0.677?.008 41 60 40 61 21 80 20 1 m s q r k m l a b c d j h i f g p n detail of lead end
79 m pd784031y remark dimensions and materials of es products are the same as those of mass-produced products. 80-pin plastic tqfp (fine pitch) (12 12 mm) item millimeters inches i j 0.5 (t.p.) 0.10 0.004 0.020 (t.p.) a note each lead centerline is located within 0.10 mm (0.004 inch) of its true position (t.p.) at maximum material condition. s a 14.00.2 0.551 +0.009 ?.008 b 12.00.2 0.472 +0.009 ?.008 c 12.00.2 0.472 +0.009 ?.008 d 14.00.2 0.551 +0.009 ?.008 f g 1.25 1.25 0.049 0.049 h 0.22 0.0090.002 p80gk-50-be9-4 s 1.27 max. 0.050 max. k 1.00.2 0.039 +0.009 ?.008 l 0.50.2 0.020 +0.008 ?.009 m 0.145 0.0060.002 n 0.10 0.004 p 1.05 0.041 q 0.050.05 0.0020.002 r 55 55 +0.05 ?.04 +0.055 ?.045 b c d j h i g f p n l k m q r detail of lead end m 61 60 41 40 21 20 1 80
80 m pd784031y 15. recommended soldering conditions this product should be soldered and mounted under the conditions recommended in the table below. for details of recommended soldering conditions, refer to the information document semiconductor device mounting technology manual (c10535e) . for soldering methods and conditions other than those recommended below, contact an nec sales representative. table 15-1. surface mounting type soldering conditions (1/2) (1) m pd784031ygc-3b9: 80-pin plastic qfp (14 14 mm, thickness 2.7 mm) soldering method soldering conditions symbol infrared reflow package peak temperature: 235 c, duration: 30 sec. max. (at 210 c or above), ir35-00-3 number of times: 3 times max. vps package peak temperature: 215 c, duration: 40 sec. max. (at 200 c or above), vp15-00-3 number of times: 3 times max. wave soldering solder bath temperature: 260 c max., duration: 10 sec. max., number of times: once, ws60-00-1 preliminary heat temperature: 120 c max. (package surface temperature) partial heating pin temperature: 300 c max. duration: 3 sec. max. (per device side) caution use of more than one soldering method should be avoided (except in the case of partial heating). (2) m pd784031ygc-8bt: 80-pin plastic qfp (14 14 mm, thickness 1.4 mm) soldering method soldering conditions symbol infrared reflow package peak temperature: 235 c, duration: 30 sec. max. (at 210 c or above), ir35-00-2 number of times: twice max. vps package peak temperature: 215 c, duration: 40 sec. max. (at 200 c or above), vp15-00-2 number of times: twice max. wave soldering solder bath temperature: 260 c max., duration: 10 sec. max., number of times: once, ws60-00-1 preliminary heat temperature: 120 c max. (package surface temperature) partial heating pin temperature: 300 c max. duration: 3 sec. max. (per device side) caution use of more than one soldering method should be avoided (except in the case of partial heating).
81 m pd784031y table 15-1. surface mounting type soldering conditions (2/2) (3) m pd784031ygk-be9: 80-pin plastic tqfp (fine pitch) (12 12 mm) soldering method soldering conditions symbol infrared reflow package peak temperature: 235 c, duration: 30 sec. max. (at 210 c or above), ir35-107-2 number of times: twice max., time limit: 7 days note (thereafter 10 hours prebaking required at 125 c) do not bake devices by packing them in non-heat resistant trays or packing materials such as magazine cases and tapes. use heat-resistant trays. vps package peak temperature: 215 c, duration: 40 sec. (at 200 c or above), vp15-107-2 number of times: twice max., time limit: 7 days note (thereafter 10 hours prebaking required at 125 c) do not bake devices by packing them in non-heat resistant trays or packing materials such as magazine cases and tapes. use heat-resistant trays. partial heating pin temperature: 300 c max. duration: 3 sec. max. (per device side) note for the storage period after dry-pack decapsulation, storage conditions are max. 25 c, 65 % rh. caution use of more than one soldering method should be avoided (except in the case of partial heating).
82 m pd784031y appendix a. development tools the following development tools are available for supporting development of a system using the m pd784031y. language processor software ra78k4 note 1 assembler package common to 78k/iv series cc78k4 note 1 c compiler package common to 78k/iv series cc78k4-l note 1 c compiler library source file common to 78k/iv series prom writing tool pg-1500 prom programmer pa-78p4026gc programmer adapter connected to pg-1500 pa-78p4038gk pa-78p4026kk pg-1500 controller note 2 pg-1500 control program debugging tool ie-784000-r in-circuit emulator common to 78k/iv subseries ie-784000-r-bk break board common to 78k/iv series ie-784038-r-em1 emulation board for evaluation of m pd784038y subseries ie-784000-r-em ie-70000-98-if-b interface adapter when pc-9800 series (except notebook type) is used as host machine ie-70000-98n-if interface adapter and cable when notebook type pc-9800 series is used as host machine ie-70000-pc-if-b interface adapter when ibm pc/at tm is used as host machine ie-78000-r-sv3 interface adapter and cable when ews is used as host machine ep-78230gc-r emulation probe for 80-pin plastic qfp (gc-3b9 and gc-8bt types) common to m pd784038y subseries ep-78054gk-r emulation probe for 80-pin plastic tqfp (fine pitch) (gk-be9 type) common to m pd784038y subseries ev-9200gc-80 socket mounted on board of target system created for 80-pin plastic qfp (gc-3b9 and gc-8bt types) tgk-080sdw adapter mounted on board of target system created for 80-pin plastic tqfp (fine pitch) (gk-be9 type) ev-9900 jig used to remove m pd78p4038ykk-t from ev-9200gc-80 sm78k4 note 3 system simulator common to 78k/iv series id78k4 note 3 integrated debugger for ie-784000-r df784038 note 4 device file for m pd784038y subseries real-time os rx78k/iv note 4 real-time os for 78k/iv series mx78k4 note 2 os for 78k/iv series
83 m pd784031y notes 1. ? pc-9800 series (ms-dos tm ) based ? ibm pc/at and compatible machine (pc dos tm , windows tm , ms-dos, ibm dos tm ) based ? hp9000 series 700 tm (hp-ux tm ) based ? sparcstation tm (sunos tm ) based ? news tm (news-os tm ) based 2. ? pc-9800 series (ms-dos) based ? ibm pc/at and compatible machine (pc dos, windows, ms-dos, ibm dos) based 3. ? pc-9800 series (ms-dos + windows) based ? ibm pc/at and compatible machine (pc dos, windows, ms-dos, ibm dos) based ? hp9000 series 700 (hp-ux) based ? sparcstation (sunos) based 4. ? pc-9800 series (ms-dos) based ? ibm pc/at and compatible machine (pc dos, windows, ms-dos, ibm dos) based ? hp9000 series 700 (hp-ux) based ? sparcstation (sunos) based remarks 1. ra78k4, cc78k4, sm78k4, and id78k4 are used in combination with df784038. 2. tgk-080sdw is manufactured by tokyo eletech corporation. consult your local nec sales representative when purchasing it.
84 m pd784031y appendix b. related documents documents related to device document name document no. english japanese m pd784031y data sheet this manual u11504j m pd784035y, 784036y, 784037y, 784038y data sheet u10741e u10741j m pd78p4038y data sheet u10742e u10742j m pd784038, 784038y subseries users manual - hardware u11316e u11316j m pd784038y subseries special function register table C u11091j 78k/iv series users manual - instruction u10905e u10905j 78k/iv series instruction table C u10594j 78k/iv series instruction set C u10595j 78k/iv series application note - software basics C u10095j documents related to development tools (users manuals) document name document no. english japanese ra78k4 assembler package operation u11334e u11334j language C u11162j ra78k series structured assembler preprocessor eeu-1402 eeu-817 cc78k4 series operation C eeu-960 language C eeu-961 cc78k series library source file C u12322j pg-1500 prom programmer eeu-1335 u11940j pg-1500 controller - pc-9800 series (ms-dos) based eeu-1291 eeu-704 pg-1500 controller - ibm pc series (pc dos) based u10540e eeu-5008 ie-784000-r eeu-1534 eeu-5004 ie-784038-r-em1 u11383e u11383j ep-78230 eeu-1515 eeu-985 ep-78054gk-r eeu-1468 eeu-932 sm78k4 system simulator - windows based reference u10093e u10093j sm78k series external part user open interface specifications u10092e u10092j id78k4 integrated debugger - windows based reference u10440e u10440j id78k4 integrated debugger - hp9000 series 700 (hp-ux) based reference to be released soon u11960j caution the above related documents are subject to change without prior notice. be sure to use the latest version when starting design.
85 m pd784031y documents related to embedded software (user?s manual) document name document no. english japanese 78k/iv series real-time os basics u10603e u10603j installation u10604e u10604j debugger C u10364j 78k/iv series os mx78k4 basics C u11779j other documents document name document no. english japanese ic package manual c10943x semiconductor device mounting technology manual c10535e c10535j quality grades on nec semiconductor devices c11531e c11531j reliability quality control on nec semiconductor device c10983e c10983j electric static discharge (esd) test C mem-539 semiconductor devices quality assurance guide mei-1202 c11893j microcomputer product series guide C u11416j caution the above related documents are subject to change without prior notice. be sure to use the latest version when starting design.
86 m pd784031y notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos device behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out- pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
87 m pd784031y nec electronics inc. (u.s.) santa clara, california tel: 800-366-9782 fax: 800-729-9288 nec electronics (germany) gmbh duesseldorf, germany tel: 0211-65 03 02 fax: 0211-65 03 490 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.1. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. united square, singapore 1130 tel: 253-8311 fax: 250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-719-2377 fax: 02-719-5951 nec do brasil s.a. sao paulo-sp, brasil tel: 011-889-1680 fax: 011-889-1689 nec electronics (germany) gmbh benelux office eindhoven, the netherlands tel: 040-2445845 fax: 040-2444580 nec electronics (france) s.a. velizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 nec electronics (france) s.a. spain office madrid, spain tel: 01-504-2787 fax: 01-504-2860 nec electronics (germany) gmbh scandinavia office taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 regional information some information contained in this document may vary from country to country. before using any nec product in your application, please contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. j96. 8
no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: standard, special, and specific. the specific quality grade applies only to devices developed based on a customer designated quality assurance program for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is standard unless otherwise specified in necs data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. anti-radioactive design is not implemented in this product. m4 96.5 caution purchase of nec i 2 c components conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. eeprom and iebus are trademarks of nec corporation. ms-dos and windows are either registered trademarks or trademarks of microsoft corporation in the united states and/or other countries. ibm dos, pc/at, and pc dos are trademarks of international business machines corporation. hp9000 series 700 and hp-ux are trademarks of hewlett-packard company. sparcstation is a trademark of sparc international, inc. sunos is a trademark of sun microsystems, inc. news and news-os are trademarks of sony corporation. the related documents indicated in this publication may include preliminary versions. however, preliminary versions are not marked as such. m pd784031y

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